1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device using magnetic memory elements.
2. Discussion of the Related Art
The rapid growth in the portable consumer product market (including the products for portable computing and communications) is driving the need for low power consumption non-volatile memory devices, with their inherent ability to retain stored information without power.
The principal technology currently available in the marketplace for these applications is EEPROM (Electrically Eraseable Programmable Read-Only Memory) technology, relying on charging (writing) or discharging (erasing) the floating-gate of a Metal-Oxide-Semiconductor (N-type) type transistor using so-called Fowler-Nordheim tunneling through the ultra-thin oxide layer of these structures. The charging of the gate creates results in an electron inversion channel in the device rendering it conductive (constituting a memory state 1). Discharging the floating gate (i.e., applying a negative bias) removes the electron from the channel and returns the device to its initial non-conductive state (i.e., memory state 0). One serious limitation to this technology is related to tunneling that limits the erase/write cycle endurance and can induce catastrophic breakdown (after a maximum of about 106 cycles). Moreover, the required charging time—which is of the order of 1 ms—is relatively long.
In order to improve performance, so-called FeRAM (Ferroelectric Random Access Memory) technology has been developed. The FeRAM memory cell consists of a bi-stable capacitor, and is comprised of a ferroelectric thin film that contains polarizable electric dipoles. These dipoles, analogous to the magnetic moments in a ferroemagnetic material, respond to an applied electric field to create a net polarization in the direction of the applied field. A hysteresis loop for sweeping the applied field from positive to negative field defines the characteristics of the material. On removing the applied field, the ferroelectric material can retain a polarization known as the remnant polarization, serving as the basis for storing information in a non-volatile fashion. FeRAM would appear to be a promising technology with good future potential since relatively low voltages (typically about 5V) are required for switching as compared with about 12 to 15V for EEPROM. Moreover, FeRAM devices show 108 to 1010 cycle write endurance compared with about 106 for EEPROM, and the switching of the electrical polarization requires as little as about 100 ns compared with about 1 ms for charging an EEPROM. However, the need for an additional cycle to return a given bit to its original state for reading purposes aggravates the problems of dielectric fatigue. This, in turn, is characterized by degradation in the ability to polarize the material. In addition, owing to the behavior of these materials about their Curie temperature, as well as compositional stability (and associated changes in Curie temperature), even moderate thermal cycling promotes accelerated fatigue. Finally, fabrication process uniformity and control still remains a challenge.
Today, MRAM (Magnetoresistance Random Access Memory)—whose development began some 20 years ago—appears to hold the greatest promise for existing technologies in terms of read/write endurance cycle and speed. The technology relies on a writing process that uses the hysteresis loop of a ferromagnetic strip, while the reading process involves the anisotropic magnetoresistance effect. Basically, this effect (based on spin-orbit interaction) relates to the variation of the resistance of a magnetic conductor, dependent on an external applied magnetic field. The bit consists of a strip of two ferromagnetic films (e.g., NiFe) sandwiching a poor conductor (e.g., TaN), placed underneath an orthogonal conductive strip line (i.e., known as the word line). For writing, a current passes through the sandwich strip and when aided by a current in the orthogonal strip-line, the uppermost ferromagnetic layer of the sandwich strip is magnetized either clockwise, or counterclockwise. Reading is performed by measuring the magneto-resistance of the sandwich structure (i.e., by passing a current). Magneto-resistance ratios of only about 0.5% are typical, but have allowed the fabrication of a 16 Kb MRAM chip operating with write times of 100 ns (and read times of 250 ns). A 250 Kb chip was also later produced by Honeywell.
The discovery of so-called Giant Magneto-resistance (GMR) in 1989, implemented by sandwiching a copper layer with a magnetic thin film permitted further improvement in memory device performance. The GMR structures showed a magneto-resistance of about 6%, but the exchange between the magnetic layers limited how quickly the magnetization could change direction. Moreover magnetization curling from the edge of the strip imposed a limitation on the reduction in the cell size, or scaling.
Promising results were then obtained with the so called Pseudo-Spin Valve (PSV) cell made of a sandwich structure with two magnetic layers mismatched so that one layer tends to switch magnetization at a lower field than the other. The soft film is used to sense (by the magnetoresistance effect) the magnetization of the hard film—this latter film constitutes the storage media, having magnetization of either up or down (i.e., states 0 or 1). PSV structures are amenable to scaling but the reported fields required to switch the hard magnetic layer are still too high for high density integrated circuits. These devices appear to potentially represent a replacement for EEPROMs.
Further improvements in magnetoresistance (i.e., up to 40%) are obtained with spin-dependent tunneling devices (SDT). These devices are made of an insulating layer (i.e., the tunneling barrier) sandwiched between two magnetic layers. Device operation relies on the fact that the tunneling resistance, in the direction perpendicular to the stack, depends on the magnetization of the magnetic layers. The highest resistance is obtained when the magnetization of the layers is anti-parallel, and the parallel case provides the lowest resistance. The variation of spin (i.e., up or down) state density between the two magnetic layers explains this behavior. One of the layers is pinned while the second magnetic layer is free and used as the information storage media. SDT show promise for high performance non-volatile applications. Indeed there have been some reported values for write times as small as 14 ns with this approach. However, controlling the resistance uniformity (i.e., the tunneling barrier thickness and quality), and hence controlling the switching behavior from bit to bit remains a real challenge that has yet to be overcome in practical implementation. What is needed is a non-volatile memory device that is fast, reliable, relatively simple in design, inexpensive, and robust.